Content addressable memory (CAM) devices, sometimes also referred to as “associative memories”, can provide rapid matching functions between an applied data value (e.g., a comparand, compare data, or search key) and stored data values (e.g., entries). Such rapid matching functions are often utilized in routers, network switches, and the like, to process network packets.
A typical CAM device can store a number of data values in a CAM cell array. In a compare (i.e., search) operation, entries can be compared to a compare data value (i.e., key). An entry that matches the key can result in the generation of a match indication.
In a conventional CAM device, search operations can be conducted in response to a system clock, with searches being undertaken every clock cycle. As a result, CAM devices can draw considerable current as match lines in the CAM cell array are continuously charged and discharged each clock cycle.
Current draw in CAM device can be particularly problematic in the case of a “cold start” operation. A cold start operation can occur when a CAM device switches from an idle state, in which the various CAM array sections of the device are not operational, to an active state, in which CAM array sections perform various functions, such as a search operation.
Existing conventional approaches can transition from an idle state to a full active state (e.g., search) in a single cycle. This can potentially happen on every other cycle as the CAM executes requests within a system. When CAM device portions (i.e., cores or blocks) go from an idle to an active state, there can be a very large change in the current requirement for the device. In current generation parts, such a current surge can be too large for the on-chip capacitance to support and can happen too quickly for capacitors to respond on circuit boards associated with the CAM device.
Still further, parasitic inductance of a package containing a CAM device, as well as inductance inherent in a CAM device mounting arrangement can prevent a fast ramp up of the current, preventing an adequate current supply when needed by the CAM device.
The above deficiencies can result in a power supply voltage “sag” (i.e., level dip) within the CAM device. In addition, the rapid change in current (dl/dt) through parasitic inductive elements can give rise to ground “bounce” (transient jump in a low supply voltage level), which can further disturb CAM operations. These undesirable variations in supply voltages can lead to failures. Such failures are often referred to as “cold start” failures or problems.
To better understand various feature and advantages of the disclosed embodiments of the present invention, examples of other CAM device cold start operations will now be described with reference to FIGS. 6, 7A and 7B.
FIG. 6 is a block diagram of one approach for reducing overall transient current in a CAM device. In the arrangement of FIG. 6, a CAM device 600 can be divided into two halves 602-0 and 6021, with each half performing a search on opposite edges of a clock signal. In particular, on one type of clock transitions (e.g., low-to-high), one side 602-1 (SIDE B) can precharge match lines, while other side 602-0 (SIDE A) evaluates (i.e., compares a search key to data in CAM entries). On the other clock transition (e.g., high-to-low), the two sides operate in the opposite fashion
Such an arrangement can help to spread out current demand within a cycle, however, as CAM devices increase in capacity and operating speed, such an approach may not be sufficient to eliminate cold start and related problems.
A more detailed example of CAM device having alternate activation of sides according to a clock signal is shown in FIG. 7A, and designated by the general reference character 700. CAM device 700 can include a number of CAM blocks 702-1 to 702-8. The CAM blocks are arranged into one side 704-0, that includes CAM blocks (702-1 to 702-4), and into another side 704-1, that includes CAM blocks (702-5 to 702-8).
The CAM blocks of side 704-0 receive command and search key data from an input bus 706, and are commonly activated according to a first clock signal CLK. In the case of a search command, search results are latched on CLKB and output to an output latch 708.
The CAM blocks of side 704-1 can also receive command and search key data from an input bus 706. However, the CAM blocks of this side are commonly activated according to a second clock signal CLKB, which can be the inverse of the first clock signal. Results from this side 704-1 can be output to priority logic 710. In addition, same search results from the other side 704-0 can be output from output latch 708 to priority logic 710.
The operation of the arrangement of FIG. 7A is shown in FIG. 7B. FIG. 7B is a timing diagram that includes waveforms for the first and second clock signals CLK and CLKB. In addition, the state of each CAM block is shown (CAM1 to CAM8), along with a device current supply ISUPP, and change in device current ΔI.
FIG. 7B shows a CAM device going from an idle state to an active state at time t0. That is, the CAM device undergoes a “cold start” at time t0.
As shown by the ISUPP and ΔI waveforms, on a first type transition of the clock signal (CLK low-to-high), a current surge can occur as the CAM blocks of one side of the CAM device are activated. Similarly, in the next clock transition at time t1 (CLK high- to-low), a second current surge can occur. A theoretical current rate limit is shown as “Δlcollapse”. This limit represents a current surge value at which errors can occur and/or device reliability can be compromised.
The above noted current surges can cause supply dips, which in turn, can cause device failures.
One very a particular type of device failure is shown in FIGS. 8A and 8B. FIG. 8A is a block schematic diagram of a CAM entry and corresponding match detect circuitry. It is understood that such a structure is repeated numerous times within each CAM block.
FIG. 8A shows a CAM entry 800 that can include a number CAM cells commonly connected to a match line ML. A CAM entry 800 can compare a stored data value with compare data (key) CD. A match line ML can provide one input to a match sense amplifier MSA. An MSA can determine a match/no-match according to a comparison between an input voltage SAIN (which corresponds to a match line voltage) and a threshold voltage Vthresh for the MSA.
FIG. 8B shows one example of how a cold-start error can occur. FIG. 8B is a timing diagram showing a clock signal CLK, power supply levels VDD and VSS, and various sense waveforms.
The sense waveforms show a match line voltage ML, a sense input potential SAIN, as well as two sense voltage waveforms, one corresponding to an ideal case VSENSE(IDEAL), such as that when a CAM device has executed a series of sequential search operations and thus has fully “ramped-up” power supply levels. The other waveform VSENSE(COLD) corresponds to a cold start case, such as when a CAM device transitions from idle to a search operation.
Referring still to FIG. 8B, on the rising edge of clock signal CLK, one half (SIDEA) of a CAM device can precharge a match line in preparation for the search and the other half (SIDEB) of the device can execute the search. In particular, on a falling edge of the clock signal CLK, a SIDEB half precharges a match line in preparation for the next search while the SIDEA half executes the search. As shown in the figure, a current surge on each edge of clock CLK can cause a low supply VSS (e.g., ground) to rise and high supply VDD to sag. This can effectively lower a level of the ‘match’ trip point (Vthresh). This is represented by the difference in the VSENSE(IDEAL) and VSENSE(COLD) levels.
A typical CAM arrangement will have some predetermined setup time, for the latch to correctly latch the data after which match data can no longer be compared. That is, a match result value would need to be sensed and latched prior to the setup time period. FIG. 8B shows two time periods, a setup time for the ideal case Tsetup(IDEAL), which begins at time t2, and another for a cold start case Tsetup(COLD), which begins at time t3.
A comparison between the ideal and cold-start cases demonstrates how cold-start errors can occur. In the ideal case, prior to time t2, a sense node potential SAIN falls below a sense voltage VSENSE(IDEAL). This can indicate a MISS result. In contrast, in the cold start case, a sense voltage VSENSE(COLD) can remain above the level needed to indicate a miss for a longer duration. The result can be a setup time, Tsetup(COLD), that can be “pushed” out beyond the necessary setup time Tsetup for a latch. Consequently, search result logic can indicate a hit when the search actually results in a miss.
It is believed that the above-described errors are most likely to occur in the case of a single bit miss, where a single exclusive-OR (XOR) stack within one CAM cell of an entry has to discharge an entire match line. If more than one bit misses, then two or more XOR stacks can pull the match line low, and the match line can discharge much more quickly, and so is more likely to fall below a sense voltage potential prior to a setup time Tsetup.
Increases in supply current surges, like those noted above, can result in other drawbacks. When the current demand stops at the end of a long sequence of searches, the inductance of the packaging can keep current flowing, resulting in a boost in supply voltage levels. Such rises in the supply voltages can stress the gate oxide of metal-oxide-semiconductor (MOS) type transistors, increasing the possibility of oxide breakdown in such devices. In addition, such increases in supply level can lead to electromigration in conductive lines, which can lead to higher resistance signal lines, or in a worst case, opens.
Examples of approaches to clocking different portions of CAM device are disclosed in U.S. Pat. No. 6,240,000, titled CONTENT ADDRESSABLE MEMORY WITH REDUCED TRANSIENT CURRENT, issued to Sywyk et al. on May 29, 2001. Another arrangement is disclosed in commonly-owned co-pending U.S. patent application Ser. No. 10/746,899, titled STAGGERED COMPARE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORY by Om et al., filed on Dec. 24, 2003. The contents of this application are incorporated by reference herein.
In light of the above, it would be desirable to arrive at some way of reducing the peak current drawn by a CAM device when transitioning from a low activity state (e.g., idle) to a high activity state (e.g., search).
It would be desirable if such an arrangement does not decrease overall throughput of the CAM device.